An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a insulating layer such as a dielectric layer. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of second conductivity type (P or N) into a semiconductor substrate of first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide a gate which provides a mask during formation of the source and drain by ion implantation. Thereafter, a drive-in step is applied to repair crystalline damage and to drive-in and activate the implanted dopant.
Several objectives influence IGFET design and fabrication. First, there is a desire to reduce the dimensions of the IGFET. Increasing the number of individual IGFETs that can be placed onto a single silicon chip or die produces increased functionality per chip. Second, there is a continual desire is to improve performance, and particularly the speed, of the IGFET transistors. This pursuit is manifested in shorter conduction channel lengths and in efforts to obtain low contact resistivity at the IGFET junctions. These aspects offer increased IGFET speed and allow for a greater number of operations to be performed by the IGFET in less time. IGFETs are used in great quantity in computers where the push to obtain higher operation cycle speeds demands faster IGFET performance. Lastly, there exists a constant need to maintain costly IGFET fabrication steps at a minimum.
As the feature dimensions of the IGFET device decrease, new performance hurdles present themselves. One particular difficulty, concerns electrical shorts between IGFET devices and capacitive coupling between the closely stacked IGFET structures. As the IGFETS are pushed into a more dense arrangement next to one another there is a heightened tendency for stray electrical signals to pass from device to device. The stray electrical signals cause the IGFETs to malfunction or possible breakdown entirely. Spacer shells are utilized to isolate the individual IGFET devices from each other. The better the geometric configuration and material makeup of the dielectric fill the more improved the isolation properties of the spacer shell.
As shown above, a threshold point exist where heightened speed and reduced dimensions will lead to IGFET breakdown. Conventional approaches have encountered difficulty trying to maintain IGFET performance in the face of decreasing IGFET size and increasing IGFET density on the surfaces of silicon die. In the effort to overcome these hurdles, it is equally desirable to keep costly processing steps to a minimum. Thus, it is an objective to uncover new spacer shell structures which provide the needed isolation properties. It is a further objective to uncover methods to produce new spacer shell structures which facilitate increased performance and but which do not compromise the IGFET's longevity or fabrication budget.